1. Field of the Invention
This invention relates to a semiconductor device called a BGA (ball grid array) and more particularly to such a semiconductor device using a metal base substrate.
2. Description of the Related Art
In recent years BGAS have been attracting the increasing attention of the semiconductor industry as they are advantageous in increasing the number of pins or prongs and in operating at a much higher speed as compared to QFP (quad flat package) type semiconductor devices, which have been a popular conventional technology. To the end various proposals have been made up to now. The following are examples of these proposed technologies.
FIG. 12 of the accompanying drawings is a schematic cross-sectional view of a conventional semiconductor device called SBGA (superBGA) disclosed in "ELECTRONIC NEWS Jan. 22, 1996", pp. 48 (an article entitled "The Package" and written by B. Levine and F. Guinther) . This known technology is hereinafter called the first conventional art.
In the first conventional art, as shown in FIG. 12, a metal ring 812 is stuck to the back (or lower) surface of a metal substrate 801 with insulative or conductive adhesive. And an insulator film 802 is placed on the metal ring 812, and over the insulator film 802 a wiring pattern 803 is formed.
Further, the wiring pattern 803 is covered with a cover insulator film 806 over its entire back surface except a plurality of so-called land portions where solder bump contacts 805 are formed and a plurality of so-called stitch portions which are to be used for the purpose of wire bonding. The metal substrate 801 is exposed at a portion (usually called a device hole) where a silicon chip 807 is to be loaded; the silicon chip 807 is bonded to such portion using a mount 808. Then electrodes of the silicon chip 807 are connected with one end of the wiring pattern 803 by bonding wires 809. Finally the silicon chip 807 and the bonding wire 809 as well as their neighborhood are sealed with seal resin 810.
FIG. 13 of the accompanying drawings is a schematic cross-sectional view of a semiconductor device disclosed in a monthly semiconductor device technology magazine "NIKKEI MICRODEVICE JUNE 1995", pp. 61-65 (an article entitled "Packaging Technology" [literally translated] and written by H. Asakura), published by NIKKEI Business Publication, Inc., Tokyo, Japan. This known technology is hereinafter called the second conventional art.
In the second conventional art, a wiring pattern 903 is formed over an insulator film 902, and electrodes of a silicon chip 907 are bonded to one end of the wiring pattern 903. The insulating film 902 is locally cut out at a device hole where the silicon chip 907 is to be loaded. And the wiring pattern 903 is covered with a cover insulator film 906 over its entire back surface except a plurality of land portions where solder bump contacts 905 are to be formed and a plurality of stitch portions where the electrodes of the silicon chip 907 are to be bonded to the one end of the wiring pattern 903. To maintain the flatness of a prospective package, a support ring 913 is mounted on an outer periphery of the package. Finally the silicon chip 907 and its neighborhood as well are sealed with seal resin 910.
Another conventional technology on BGA is disclosed in a thesis "BGA Market Outlook" presented by TechSearch International, Inc. in "Area Array Packaging Seminar", which was held Dec. 1, 1995 at Waseda University in Tokyo, Japan under the cosponsorship of Circuit Package Society of Japan, Waseda University, Tokyo, Japan, and TechSearch International, Inc., Austin, Texas, U.S.A.. This known technology is hereinafter called the third conventional art and will now be described with reference to FIG. 14 of the accompanying drawings of the present specification.
As shown in FIG. 14, to obtain a flexible substrate, a pair of wiring patterns 1003 laid over opposite sides of an insulator film 1002 are interconnected via through holes 1014; a silicon chip 1007 is connected to one end of the wiring pattern 1003 on one side by a C4 (control collapsed chip connection) bump contact 1007a. In view of its easy handling and flatness, this flexible substrate is stuck at its periphery to a stiffener 1016 with adhesive 1017. Yet in view of heat-radiation property of the silicon chip 1007, the back surface of the silicon chip 1007 and the stiffener 1016 as well are stuck to a heat spreader 1001 with thermal-conductive adhesive 1015. On the wiring pattern 1003 on the other side, which pattern is not connected with the silicon chip 1007, a solder bump contact 1005 is formed to secure an electrical connection with the exterior. Finally the spacing between the silicon chip 1007 and the substrate is sealed with underfill resin 1010.
However, according to the first conventional art of FIG. 12, since the whole BGA is covered with the metal substrate, it is impossible to visually inspect the status of formation of the solder bump contacts after this semiconductor device has been loaded on the substrate to complete the package, so package inspection can no longer be performed. The same may be said of the third conventional art of FIG. 14, in which the whole package is covered with the heat spreader.
Again in the first conventional art, there is a difference in coefficient of thermal expansion between the material to be used as the substrate and the metal to be used in the package and therefore a thermal stress exerts on the solder bump contacts due to the variation of temperature. As a result, the solder bump contacts would be depleted with the lapse of time to cause only a limited reliability of mounting the package onto the mother board.
Further, in each of the first to third conventional arts, since the metal substrate, the heat sink, the stiffener and the support ring are stuck one by one to the wiring pattern in individually processed form, handling would be meticulous and the number of process steps and parts would be increased, thus increasing the cost of production.
Still further, in the second conventional art, it would be difficult to efficiently radiate heat that has been generated in the silicon chip. Furthermore, since only the wiring pattern is a conductive layer, it would also be difficult to realize stabilized signal wiring and reduction of possible noises by stabilizing either the ground wiring or the power supply wiring mechanically.